July 2nd, 2017 ~ by admin

ITT AN/ALQ-136 Countermeasures Processor – Bit Slice with a Bite

ITT 80063SM-A-919797 – AN/ALQ-136(V)I Processor. The 2901B’s are the 4 larger dies in a row, middle right.

Military computing applications require many custom designs, as they are very mission specific.  A great example is this ITT hybrid processor.  It was designed and used for the AN/ALQ-136(V)1 CMS (CounterMeasures System) for the AH-1F Cobra Attack helicopter.  Two of these hybrids are used in the system, one for the Mod Recovery board, and one for the SLO processor board.  These boards are used to detect hostile pulse RADAR systems, analyze them, and begin jamming based on what type they are.

This requires relatively fast processing, and a generally custom design.  Today a modern DSP processor could handle this task without issue.  However in the early 80’s (the AN/ALQ-136 debuted in 1982) DSP processors were in their infancy.  In 1982 a fast custom processor needed to be built with bit-slice elements.  In this case the very versatile AMD 2901 was used.  The ITT hybrid integrates 4 AMD AM2901B processor dies, as well as associated memory and interfacing elements.  The single package contains almost 100 dies, and many discrete components.  It is built on a ceramic substrate with gold traces, and sealed in a metal package.  This is required to protect the digital components of the system from electronic interference, whether from external sources, or from the helicopters own RADAR systems.  The AN/ALQ-136 is designed to prevent the Cobra from being successfully targeted by RADAR guided missiles, failure means a strong possibility that the helicopter gets hit, not something its crew would like to deal with.

4x AMD AM2901B Dies.

The 4 AMD 2901Bs run at 16MHz (50% faster then the original 2901s) and are made with ECL; together they provide 16-bit processing of the incoming RADAR signals. The SLO (Side Lobe Opposition) and MOD Recovery (Modulation Recovery) are used to determine the exact type of the enemy RADAR.  Each RADAR has a distinct characteristic that the CMS can match and respond to.  The CMS is programmed to respond to the radar signals of the most critical threat weapon systems anticipated to be encoun

Israeli AH-1F Cobras – Now Retired/Transferred to Jordan.

tered in the hostile environment.  These signatures are stored in the hybrids ROMs as well as the desired response to them.  Updates likely remain replacing these hybrids with updated versions.  New countermeasures systems (such as the 136’s replacement, the AN/ALQ-211) are more easily upgradeable to new threats.

The AH-1F Cobra continues to fly with the air forces of several countries around the world, notably Pakistan, Jordan, and Turkey.  The United States Forest Service also operates 25 AH-1F Cobras for wildland fire use, but it is rather unlikely that the countermeasures on these are operable, let alone needed.

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June 20th, 2017 ~ by admin

Intel’s First: The 3101 64-bit Bipolar Memory

Intel 3101 Memories, from late 1969 early 1970.

Today when we think of Intel, the ‘processor company’ comes to mind.  It was now what they are best known for, but when Intel began in 1969 they did not make processors, they made memory, specifically SRAM, DRAM, and EPROMs.  The very first product Intel released, in April of 1969, was the 3101 64-bit SRAM.  It was made on the new, and fast Schottky Bipolar process.  This made it very fast (access times of 60ns) but very power hungry.  It dissipated 525mW, over half a watt, for 64-bits of memory.

Two months later Intel released the 1101, which was developed at the same time as the 3101.  It was made on a PMOS process, which allows much greater densities, the 1101 was 256-bit SRAM chip.  The sacrifice is speed, the 1101 is a bit slow, with access times of around 1.5us.  Operating power was 700mW but in standby mode it only drew 350mW.

Very Early Burroughs “D” NanoMemory board with 32 Intel 3101 memories (picture from Evan Wasserman )

Computer makers were eager for single chip memories, they allowed for more dense memory systems.  One of the first users of the 3101 was Burroughs in their ‘D’ machine, a computer designed for the Air Force in 1969.  It used 3101s for its ‘nanomemory’ organized as 64×56 bits (needing 56 3101s if they were used for all the nanomemory.  Other notable users was in implementing the stack in the Datapoint 2200.  The 2200 is the grandfather of x86, its architecture was the basis for the Intel i8008, which then led to the 8080 and 8086 processors.  The first Xerox Alto’s also used the Intel 3101, arguably the first GUI implementation.

The 3101 evolved as Intel learned the process of making chips, and assembling them.  This is notable in looking at die shots of two 3101s with lot codes likely only a few months apart.  Ken Shirriff, a fellow collector, was donated a pair of 3101s nearly identical to those pictured, for decapping and die shots, by Evan Wasserman (who donated several to the CPU Shack Museum as well).  If addition to the package difference (not the larger lid on the later one) there is some die changes as well.  The bonding pads were made much larger, likely to ease the assembly, and the main VCC line on the top of the die was made smaller.  Connections to bond pads were also cleaned up and refined.  The logic of the device appears unchanged.

3101 dies. Left is lot 898, right is the later 1116. Click for much larger version. Die photos provided by Ken Shirriff

Through the 1970’s and well into the 1980’s memory devices were by far Intel’s largest revenue source.  It wasn’t until fierce competition in the memory market that this changed.  Had it not been for IBM adopting x86, things could have been much different and more difficult for Intel.  The rapid adoption of x86 gave Intel a new revenue stream, and one that was less likely to be pressured by commodification as was happening to memory devices.



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June 5th, 2017 ~ by admin

SiFive FE310: Setting The RISC Free

SiFive FE310 RISC-V Processor. Early LSI SPARC Processor for size comparison. Both are based on U.C. Berkeley RISC designs.

The idea of RISC (Reduced Instruction Set Computer) processors began in education, specifically University of California, Berkeley in the early 1980’s, and it was out universities that some of the most famous RISC designs came.  MIPS, still in use today, started life as a project at Stanford University, and SPARC, made famous by Sun, and now made by Oracle and Fujitsu, started life as a Berkeley University project.  Universities have continued to work with RISC architectures, for research and teaching.  The simplicity of RISC makes them an ideal educational tool for learning how computers/processors function at their basic levels.

By the late 1980’s RISC had begun to become a commercial revolution, with nearly every player having their own RISC design.  AMD (29k), Intel (i960), HP (PA-RISC), Weitek (XL8000), MIPS, SPARC, ARM, Hitachi (SH-RISC), IBM (POWER), and others offered their take on the RISC design.  Most were proprietary, while a few were licenseable, none were open architectures for anyone to use.

Unfortunately, outside of the university, RISC processors are not as simple.  The architectures, and their use may be, but licensing them for the design is not.  It can often take more time and effort to license a modern RISC processor then it does to actually implement it.  The costs to use these architectures,both in time and money often prohibit their very use.

SiFive FE310 – Sample Donated by SiFive. Full 32-bit RISC on a 7.2mm2 die in a ~36mm2 package

It is out of this that SiFive began.  SiFive was founded by the creators of the first commercially successful open RISC architecture, known as RISC-V.  RISC-V was developed at Berkeley, fittingly, in 2010 and was designed to be a truly useful, general purpose RISC processor, easy to design with, easy to code for, and with enough features to be commercially useful, not limited to the classroom.  It is called the RISC-V because it is the fifth RISC design developed at Berkeley, RISC I and RISC II being designed in 1981, followed by SOAR (Smalltalk On A RISC) in 1984 and SPUR (Symbolic Processing Using RISC) in 1988.  RISC-V has already proved to be a success, it is licensed freely, and in a way (BSD license) that allows products that use it to be either open, or proprietary.  One of the more well known users is Nvidia, which announced they are replacing their own proprietary FALCON processors (used in their GPUs and Tegra processors) with RISC-V.  Samsung, Qualcomm, and others are already using RISC-V.  These cores are often so deeply embedded that their existence goes without mention, but they are there, working in the background to make whatever tech needs to work, work.

The RISC-V architecture supports 122 instructions, 98 of which are common to almost all prior RISC designs and 18 common to a few.  Six completely new instructions were added to handle unique attributes of the architecture (using a 64-bit Performance Register in a 32-bit arch.) and to support a more powerful sign-injection instruction (which can be used for absolute value, among other things). It uses 31 32-bit registers (Register 0 is reserved for holding the constant ‘0’) with optional support for 32 floating point registers.  True to the RISC design, it is a pure Load/Store processor, the only accesses to memory are via the Load/Store instructions.

Intel 4004 with 5 SiFive RISC Processors. The 4004 was meant for a calculator. The FE310 is meant for whatever your mind may dream up.

SiFive is unique among RISC IP companies.  They not only license IP but also sell processors and dev boards.  The FE310 (Freedom Everywhere 310) is a 320MHz RISC-V architecture with 16K of I-cache and 16K of scratchpad RAM fabbed by TSMC on a 180nm process. Even on this process, which is now a commodity process, the FE310’s efficient design results in a die size of only 2.65mm x 2.72mm.  On a standard 200mm wafer , this results in 3500 die per wafer, greatly helping lower the cost.  Its an impressive chip, and one that is completely open source.  What is more impressive is licensing SiFive cores, it is a simple and straightforward process.  The core (32 bit E31 or 64-bit E51) can be configured on SiFive’s site, with pricing shown as you go.  The license is a simple 7 page document that can be signed and submitted online.  Pricing starts at $275,000 and is a one time fee, there are no continuing royalty payments.  The entire process can be completed in a week or less.

In comparison, ARM, the biggest licensor of RISC processors, does not publish pricing, charges 1-2% royalties on every chip made, and has a license process that can take over a year.  The base fees start at around $1 million and go into the 10’s of millions, depending on how you want to use the IP, where it will be, and for how long.  For many small companies and users this is simply not feasible, and it is these smaller users that SiFive wishes to work with.  Licensing a processor for the next great tech, should not be the hurdle that it has become.  Many great ideas never make it to fruition due to these roadblocks.  We look forward to finding SiFive processors and cores in all sorts of products in the future.

Thanks to SiFive for their generous donation of several FE310 processors to the CPU Shack Museum.

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May 14th, 2017 ~ by admin

SESCOSEM and the French 6800

SESCOSEM SFF96800K – Dated 7651 and made by Motorola

Sescosem was a French company that was formed during the merger of Thomson-Brandt and CSF in 1968.  Thomson-Brandt has its roots as a French subsidiary of GE back in 1892 as Compagnie Française Thomson-Houston (CFTH), while CSF was a French electronics company founded in 1918.  Thomson’s SESCO division (itself a joint venture between Thomson and General Electric) was merged with CSF’s COSEM division to form SESCOSEM.  SESCOSEM made many semiconductor products for the European market, starting with basic transistors and eventually second-sourcing microprocessors.

Sescosem SFF71708K – Mid 1978 – 2708 EPROM – Note the SESCOSEM logo

SESCOSEM began to work as a second-source for Motorola in September 1976.  Somewhat unusually SESCOSEM did not originally manufacture the IC’s they sold.  They received completed devices from Motorola, and remarked them as their own.  This may sound odd, but it served a purpose, it increased SESCOSEM’s market, and allowed Motorola to more easily sell their devices in Europe.  Buying local, to support the domestic industry, was, and continues to be important in Europe, so buying ‘Motorola’ devices, made in the US was less appealing then buying a ‘local’ chip, despite that chip simply being remarked. The agreement called for Motorola to supply
masks and information concerning the 6800 to Thomson-CSF (SESCOSEM parent) for present and future microprocessor products.  Eventually SESCOSEM was able to begin making their own devices at their 2 production facilities: Saint-Égrève , near Grenoble (COSEM site) and Aix-en-Provence (SESCO site).

Sescosem SFF71708J – Another 2708 but made in late 1979, note the switch to the Thomson Semiconductor logo

SESCOSEM also made/sold the various support products for the 6800 series, as well as several EPROM’s, including a clone of the 1702, 2708 and 2716. In mid-1979 SESCOSEM stopped using their own logo, and switched to that of Thomson and in 1982 SESCOSEM was rolled into Thomson Semiconductor, as the French government nationalized and consolidated many industries in an attempt to increase profitability.  Thomson Semiconductor also included Mostek (sold to Thomson in 1985), Silec,  Eurotechnique (French-National Semi joint venture) and EFCIS.  This allowed Thomson to produce Motorola designs, now including the 68000 series of processors. In 1987 SGS of Italy, merged with Thomson to form SGS-Thomson, what is now known today as STMicroelectronics.

While a bit convoluted, this is one reason so many companies manufactured Motorola products.  This helped contribute to the world-wide success of Motorola products.  No longer were they only a US product, but a global product, made and sold by global companies.  In a twist of irony, Freescale, the semiconductor portion of Motorola, was purchased by NXP Semiconductors of the Netherlands in 2015, adding yet another brand of 6800 and 68000 processors.  Only a year later however, in October of 2016 Qualcomm, one of the leading makers of cell-phone chipsets, announced that it will be purchasing NXP.  A Qualcomm 68k processor may very well be in our future.

April 13th, 2017 ~ by admin

Zycad: Emulating Hardware on Hardware

Zycad IU – Interface Control Processor for the XP series of Emulators. Fab’d by LSI in 1990

Zycad was founded in 1981 to develop and market simulation acceleration technology.  This was to allow new chip designs to be tested/simulated before being laid out in silicon, providing the possibility to catch faults earlier in the design process.  The earlier faults can be caught, the easier, and less expensive they are to fix.

By the late 1980’s Zycad a leader in simulation tech and set the standard for simulation systems.  They provided the simulation software environment, a simulation/hardware descriptive language (Zycad Intermediate Format), as well as custom hardware accelerators for the logic/fault simulation.

In 1987 Zycad shipped a customized system to LSI, which LSI was then able to use, and market for all their customer designs, notable the LSI version of the SPARC processor.  This close relationship with LSI also benefited Zycad, as it was LSI who fab’d Zycad’s custom silicon, the heart of their emulation system. In the late 80’s and early 90’s the main Zycad emulation system was the XP series.  The XP series (consisting of the 100, 140 and 200) was based on 2 main IC’s.  The Interface Control Processor (IU) was the interface between the host processor (either a SPARC system, or a VAX type workstation) and the Logic/Fault Emulation Processors (PU’s).  One IU could control multiple PU’s and a typical system (such as the XP-140) had 1 IU and 5 PU’s.  These systems could emulate from 256,000 (XP-100) to 4 million (XP-200) gates at speeds from 2.5 millions events/sec to 40 million events/sec.

Zycad XP-140 system board with 1x IU and 5x PU Emulation processors

In 1996 Zycad announced the Lightspeed simulation server, massively parallel simulation server running on from 64-4096 processors, each with their own on chip memory.  These were implemented on 0.5u ASICs from LSI.  This technology was sold later that year to one of Zycad’s competitors, IKOS, leaving Zycad to enter the field of FPGAs as Gatefield, which later would be bought out by Actel.  IKOS was later acquired by Mentor Graphics, a company that worked extensively with Zycad and their emulators in the 1980’s and 1990’s.  The customer, had now become the owner.

What Zycad began in the 1980’s continues today on a massive scale.  The XP series and the later Lightspeed simulation server are in many ways similar to the Palladium and Palladium II processors by Quickturn/Cadence that we discussed lat year.

Hardware simulation is a field that continues to grow in scale and complexity.  As systems become more and more complex, transistors counts continue to rise, and the need to make sure it works, before putting it in silicon remains.

March 29th, 2017 ~ by admin

TeraNex: Filling the GAPP

Teranex Piranha TN3260B – 1024 PE Array @ 64-90MHz

The GAPP (Geometric Arithmetic Parallel Processor) was designed in 1981 at Martin Marietta, which later became Lockheed Martin Electronics & Missiles.  It was funding in large part by the US Dept. of Defense as a way to develop technologies for ultra high-speed image processing.  There was a strong need for image processing, in near real time for military applications, in particular pattern recognition.  Being able to process a moving image and match its features to known patterns was very useful for targeting of many weapons system.

The GAPP processor was a massively parallel SIMD (Single Instruction Multiple Data) processor.  SIMD works very well on large sets of data that are processed in the same way.  In the design of GAPP, this data set was the 2D-array of an image, or frame, from a video.  The GAPP is at its core a very large array of simple processors, called processor elements (PE).  Each PE is relatively simple, containing a single bit ALU and registers/memory.  Each PE handles a single pixel of the image/frame, and is connected in a 2-D mesh to its 4 nearest neighbors.  This allows arrays of these PE’s to scale very well.  By 1992 Lockheed had GAPP systems with 82,944 elements and by the 2000’s systems were available with nearly 300,000.

In 1998 TeraNex was formed to commercialize this technology, and in 1998 there was a looming problem in television, one that the GAPP, and newly formed TeraNex were well suited to solve.

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March 15th, 2017 ~ by admin

MC6801/6803 Expansion Now Available for the 680x/650x Test System

6801/6803 Expansion Board and PCP

After several months of development an expansion for the 680x/650x Test system is now available to support the very popular and widely used 6801 and 6803 MCUs.  The Motorola 6801 was one of the first (with the 6802) MCU’s that Motorola made based on the MC6800 8-bit processor.  It includes RAM/ROM, Serial I/O and timers.  The test board tests the function of the base CPU, the timers/data capture, and the Serial I/O.  The MC6803 is a 6801 without the built-in ROM and with less I/O.

The expansion supports both types as well as their copies/derivatives made by Hitachi, Fujitsu, SGS and others.  The expansion is included in the complete 680x/650x Test system, bringing its total supported processors to well over 35.  The expansion does require updated firmware, which is included in all new systems (and available to upgrade previously sold systems.)

March 12th, 2017 ~ by admin

When Intel Runs out of Chips…..

Intel D80130-3 OSP – Engineering Sample – Early 1982

A seemingly impossible occurrence today, but something that Intel has faced in the past.  It is common for customers to need chips that are no longer in production, either for repair of legacy systems, or to keep an old but reliable design in production.  Typically these parts can be sourced on the secondary market, or from End-of-Life suppliers such as REI, or InnovASIC.  But what happens when Intel themselves needs a chip that they previously made, but no longer do?

Such was the case with the 80130 Operating System Processor.  The 80130 was a co-processor designed in 1981, to make use of Intel’s high-density ROM capabilities.  The 80130 contained 16K of ROM, 3 timers (compatible with 8254), an interrupt controller (similar to the 8259), and a baud-rate generator.  It was capable of bus management and control and could directly control an 8087 FPU as well.  These are designed to work with the 8086/88 and 80186/188 processors.  The 16K of ROM was coded with 35 Operating System primitives (a subset actually of the Intel iRMX86 RTOS (Real Time Operating System).  This firmware allowed easier support for the constructs typically used in a multitasking OS.  Essentially the 80130 extended the instruction set of the x86 to include higher level OS functions.

Intel D80130-2 – 1983 – Production version (though datasheets continued to be marked ‘Preliminary’ though its entire life)

The original version, called (for no known reason) the 80130-3 was released in engineering sample versions only.  It could run at up to 8MHz allowing it to work with any of the x86 processors of the time.  After some small timing adjustments, the 80130 was released to production as the 80130-2, still keeping with the 8MHz max.  Later references show a 80130 at 5MHz as well as the 8MHz -2 part.  However, the 5MHz part has not been seen (as of this writing) and is likely to exist only in datasheets.

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February 26th, 2017 ~ by admin

Aeroflex UT80CRH196KDS – The MCS-196 Goes to Space

Aeroflex 5962F0252301VXA = UT80CRH196KDS
F = 3×105 Rad
01 = Mil Temp (-55C-125C)
V = Class V

The MCS-196 is the second generation of Intel’s MCS-96 family of 16-bit processors.  These are a control oriented processor originally developed between Ford Electronics, and Intel in 1980 as the 8060/8061 and used for over a decade in Ford engine computers.  They include such things as timers, ADC’s, high-speed I/O and PWM outputs.  This makes them well suited for forming the basis of applications requiring control of mechanical components (such as Motors, servos, etc).  The 196KD is a 20MHz CMOS device with 1000 bytes of on die scratch pad SRAM. The UT80CRH196KDS (unqualified/not tested for radiation) is priced at $1895.00 in quantities of 5,000-10,000 pieces (in 2002). Fully qualified ones will of course cost a lot more. The KDS is a drop in replacement for the previous KD version, which only supported doses of 100krads.

This obviously lends itself to automotive applications, hard disk control, printers, and industrial applications.  There is however, another application they have found wide spread use in, spacecraft.  Spacecraft are not all to different from a car in the amount of mechanical systems that must be interfaced to the computer controls.  The difference however, is that unlike your car, spacecraft electronics must work, always.  If a car fails, its an annoyance, if a spacecraft fails, it has the potential to cost millions of dollars, not to mention the loss of a mission.  If that spacecraft happens to be the launch vehicle, a failure can directly result in a loss of life.

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February 19th, 2017 ~ by admin

Milandr K1986VE91T – The ARM of Russia

Milandr K1986VE91T – 80MHz ARM Cortex-M3

In the early 1990’s a Milandr was formed in Zelenograd, Russia (just a short distance to the NW of Moscow), the silicon valley of Russia, home to the Angstrem, and Micron IC design houses. They are a fabless company, though with their own packaging/test facilities, specializing in high reliability metal/ceramic packages. Most of their products are fab’d in Germany, by X-Fab.  X-Fab was formed in part, from the remains of the Soviet/E. German era VEB Mikroelektronik Karl Marx, in Erfurt Germany, also known as FWE/MME and later Thesys.  In Soviet times it wasn’t uncommon for Soviet companies to use dies produced by FWE in their own packages, so this bit of legacy continues today.

The K1986VE91T is one of Milandr’s top end products, it is an 80MHz ARM Cortex-M3 based processor, and likely one of the largest, if not the largest, Cortex-M3 made.  It is made on a 180nm process and includes 32K RAM, 128K FlashROM, 96 USER I/O, USB, 2 UART and 12-bit DAC/ADC.  Judging by the die, the processor was built with standard licensed blocks, very common for such designs.  Milandr licensed the ARM Cortex-M3 itself in December of 2008, for use mainly in automotive and industrial applications. Milandr is also the very first Russian company to license and use an ARM core.

Analog Devices ADUCM322BBCZ ARM Cortex-M3 80MHz – Same basic core, but in a very much less appealing package

The package, however, is completely unique.  It is a 132 pin CQFP package. There are 33 gold leads on each side of the white ceramic package.  Each row is actually 2 staggered rows, the offset allows the finer lead pitch, and still room to bond the leads to the top of the package.  Soviet processors were often delivered in the most stunning of packages and 25 years later, Milandr keeps that tradition alive.

Each of these processors came with a brief datasheet, complete with inspection stamps for the processor. It is all in Russian, but check it out here.

Milandr made several variations of the Cortex-M3, including the VE92 and VE93 which are internally identical, but with much less I/O available owing to there smaller 64 pin and 48 pin packages respectively. Milandr also made a copy of the PIC17 processor that we covered last year.

A version of the K1986VExx continues to be made by Milandr, but renamed to the MDR32F9Qx.  It continues to have the same basic core, but in a 144 pin package, allowing even greater I/O support.